lp m 90 2 2 - 01 jun . - 20 14 email: marketing@lowpowersemi.com www.lowpowersemi.com page 1 of 4 preliminary datasheet lpm 9 0 2 2 dual n - channel enhancement power mosfet general description the lpm 9022 integrates two n - channel enhancement mos f et transistor. it u ses advanced trench technology and design to provide excellent r ds(on) with low gate charge. this device is suitable for us ing in dc - dc conversion, power switch and charging circuit. standard product LPM9022 is pb - free and halogen - free. order information lpm 90 2 2 f: pb - free package type qv: dfn - 6l pin configurations features ? trench technology ? single nmos: v d s = 2 0v, i d = 6 a r d s(on) < 26 m @ v gs = 2.5 v r d s(on) < 20 m @ v gs = 4.5 v ? super high density cell design ? extremely low threshold voltage ? small package dfn - 6l 2*3mm applications ? driver for relay, solenoid, motor, led etc. ? dc - dc converter circuit ? power switch ? load switch ? charging marking information device marking package shipping LPM9022 dfn - 6l 3k/reel pin descri p tion pin number pin description 1 ,2 source of nmos1 3 gate of nmos1 4 gate of nmos2 5,6 source of nmos2 bottom pad drain of both nmos s 1 s 1 g 1 s 2 s 2 g 2 1 2 3 4 5 6 d 1 / 2 p a d s 1 s 2 g 2 g 1 d 1 / 2
lp m 90 2 2 - 01 jun . - 20 14 email: marketing@lowpowersemi.com www.lowpowersemi.com page 2 of 4 preliminary datasheet lpm 9 0 2 2 absolute maximum ratings parameter symbol LPM9022 unit drain - source voltage v ds 20 v gate - source voltage v gs 10 continuous drain current ta=25 c 12 a maximum power dissipation ta=25 c 1.6 w operating junction temperature t j - 40 to 150 c lead temperature t l 260 c storage temperature range t stg - 55 to 150 c thermal resistance ratings parameter symbol LPM9022 unit junction - to - ambient thermal resistance steady state r j a 80 /w
lp m 90 2 2 - 01 jun . - 20 14 email: marketing@lowpowersemi.com www.lowpowersemi.com page 3 of 4 preliminary datasheet lpm 9 0 2 2 electrical characteristics parameter symbol test condition min typ . max units off characteristics drain - to - source breakdown voltage bv dss v gs = 0 v, i d =250ua 20 v zero gate voltage drain current i dss v ds = 20 v, v gs = 0v 500 n a gate - to - source leakage current i gss v ds = 0 v, v gs = 10 v 100 na on characteristics note c gate threshold voltage v gs(th) v gs = v ds , i d =250ua 0.4 0.95 v drain - to - source on - resistance r ds(on) v gs = 2.5 v 26 m v gs = 4.5 v, i d = 6 a 20 forward transconductance g fs v ds = 2.5 v, i d = 6 a 4 s capacitances, charges note d input capacitance c iss v gs = 0v, f =1.0mhz v ds = 15 v 1 550 pf output capacitance c oss 300 reverse transfer capacitance c rss 1 80 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v, i d = 6 a 13 nc gate - to - source charge q gs 5.5 gate - to - drain charge q gd 3.5 switching characteristics note d turn - on delay time t d(on) v gs = 10 v, v d d = 20 v, i d = 1.0 a, r g =6 30 ns rise time t r 20 turn - off delay time t d(off) 100 fall time t f 80 body diode characteristics forward voltage (note c ) v sd v gs = 0 v, i s = 1 a 0.2 1.0 v note a . pulse width limited by maximum junction temperature. b . surface mounted on fr4 board, t 10s. c . pulse width< 2 9 5 s, duty cycle<2% . d . guaranteed by design, not subject to production .
lp m 90 2 2 - 01 jun . - 20 14 email: marketing@lowpowersemi.com www.lowpowersemi.com page 4 of 4 preliminary datasheet lpm 9 0 2 2 packag ing information
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